MOS FETs universally are used in analog, discrete time signal processing circuits due to their nearly ideal switching characteristics. Applications include voltage sampling circuits such as discrete-to-continuous time interface circuits and switched-capacitor circuits, such as those used in analog-to-digital converters [ADCs]. In all of these sampling circuits, MOS switches are used to couple signals onto capacitive storage elements. These switches may be turned "on" and "off" by controlling the voltage on their gate electrodes. In order to turn the switches "on", the voltage between the gate and source electrodes (Vgs) must exceed the threshold voltage (Vt) of the transistor.
One common implementation of a MOS switch, a transmission gate, includes a PMOS and NMOS transistor connected in parallel, with complementary gate drive signals that swing from one supply rail to the other. The switch turns "on" when the NMOS gate is high and the PMOS gate is low, and the switch turns "off" when the NMOS gate is low and the PMOS gate is high. This simple operation allows the switch to be operated in as few as two clock phases, without requiring any intervening phases that would reduce the time available for operation of the sampling circuit (i.e., for charging and discharging the capacitive storage elements).
The "on" resistance of the transmission gate increases with decreasing supply voltage (i.e. decreased gate drive voltage). A large switch "on" resistance typically increases the settling time of the sampling circuits: the combination of the MOS switch resistance and the capacitance of the capacitive storage elements results in an RC settling time-constant associated with each capacitor. Furthermore, as is well known, when the transmission gate is turned "on", the resistance of the switch is a nonlinear function of the signal voltage coupled by the switch. With rapidly changing signal voltages, this nonlinear "on" resistance leads to distortion of the signal coupled onto the storage capacitor. Making the "on" resistance of the switch low, and/or making the "on" resistance of the switch constant (i.e., independent of signal voltage), will lead to reduced distortion of the coupled signal.
Modern advancements in MOS processing techniques continue to provide smaller MOS FET device geometries. Smaller device geometries advantageously yield smaller parasitic capacitances; however, as device geometries decrease, a corresponding reduction is required in the supply voltage due to lower breakdown voltages in the devices. For example, as a MOS transistor process size decreases from 0.6 micron to 0.3 micron, the supply voltage rating may typically decrease from 5 volts to 3 volts, respectively.
As the supply voltage is decreased, it becomes more difficult to maintain low "on" resistance in MOS FET switching devices. A smaller gate drive voltage signal swing provides smaller Vgs in the switching devices. This increases the "on" resistance of the switching transistors and thereby increases distortion and settling time. Therefore as the supply voltage is decreased, techniques must be developed to increase the gate drive beyond the supply rail to maintain a low "on" resistance.
One prior art circuit aimed at increasing the gate drive voltage signal swing is called a "clock doubler" circuit, such as that described in a 10-Bit, 20-MS/s, 35-mW Pipeline A/D Converter, by Thomas Cho and Paul Grey, Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, IEEE 1994 Custom Integrated Circuits Conference. This circuit operates to increase the clock signal (i.e., the switch gate drive signal) to approximately twice the supply voltage.
While clock doubler circuits may be made to operate reliably, such circuits may stress the breakdown limits of the switching transistors. In particular, the applicants herein have discovered that clock doubler circuits do not work reliably in smaller geometry processes because the double amplitude gate drive voltages produced by clock doubler circuits will exceed breakdown voltages of the switching transistors.
There also exist a number of prior art circuits aimed at maintaining a relatively low and constant MOS transistor device "on" resistance, each circuit having its own drawbacks or limitations. One such circuit is that described in U.S. Pat. No. 5,084,634 to Gorecki. The Gorecki circuit is directed for use in a continuous-to-discrete time sampling circuit employing a MOS transistor device that receives an input voltage to be sampled. In four clock phases, a bootstrap capacitor is charged and the voltage on one plate thereof is boosted. At the end of the four phases, a boosted version of the input voltage is provided as the gate drive voltage to the MOS transistor device in an attempt to maintain the "on" resistance thereof constant. One significant limitation with Gorecki is that its operation requires four clock phases. Furthermore, the Gorecki circuit will not work reliably with smaller geometry processes because the large amplitude gate drive voltages produced by the circuit will exceed breakdown voltages of the switching transistors.
Another prior art circuit aimed at maintaining constant "on" resistance of a MOS transistor switch is that described in U.S. Pat. No. 5,500,612 to Sauer. Like Gorecki, the Sauer circuit bootstraps the gate drive of the transistor switch to a boosted level of the input voltage. A limitation of the Sauer circuit is that its operation requires three clock phases. An additional limitation is that Sauer employs a transmission gate switch which has a nonlinear parasitic capacitance that will distort the coupled input signal.
A further prior art circuit aimed at maintaining constant "on" resistance of a MOS transistor switch is that described in U.S. Pat. No. 5,170,075 to deWit. Like Gorecki and Sauer, deWit ties the gate drive voltage of the MOS transistor switch to a boosted level of the input voltage. A drawback of deWit is that deWit does nothing to ensure that the gate drive voltage does not exceed the breakdown voltage of the transistor. In addition, like Sauer, a transmission gate switch is employed, which has a nonlinear parasitic capacitance that will distort the coupled input signal.
It is a general object of the present invention to provide a circuit and method for producing an improved MOS FET switch. The improved MOS FET switch disclosed herein operates on only two clock phases, enabling higher speed operation, provides a nearly constant "on" resistance and parasitic capacitance to reduce distortion, and avoids stressing any devices beyond their breakdown voltages making it suitable for use on smaller geometry processes.